"Implementing a Highly Parameterized Digital PIV System On Reconfigurable Hardware"

 PhD Dissertation by Abderrahmane Bennis, 2010


Committee:  Professor Miriam Leeser (Advisor), Professor Gilead Tadmor, and Professor
Russ Tedrake of MIT.

Abstract:

Parameterization of circuits is increasingly in demand. It opens the door both for
investigating the right parameters for different application domains and reuse of
components with the specific parameters in building new custom hardware. This can
significantly reduce the time to market. In this work, we investigate the
parameterization of particle image velocimetry (PIV), a technique that is used in many
engineering domains.

This dissertation presents PARPIV, the design and prototyping of a highly parameterized
digital PIV system implemented on reconfigurable hardware. Despite many improvements to
PIV methods over the last twenty years, PIV post-processing remains a computationally
intensive task. It becomes a serious bottleneck as camera acquisition rates reach 1000
frames per second. In addition, for different engineering applications, different PIV
parameters are required. Up to now, there has been no PIV system that combines both
flexible parameterization and high computational performance. In our research we have
created such a system. This implementation is highly parameterized, supporting
adaptation to a variety of setups and application domains. The circuit is parameterized
by the dimensions of the captured images as well as the dimensions of the interrogation
windows and sub-areas, pixel representation, board memory width, displacement and
overlap. Through this work, a parameterized library of different VHDL components was
built. To the best of the authors’ knowledge, this is the first highly parameterized PIV
system implemented on reconfigurable hardware reported in the literature. We report on
the speedup in hardware over a standard software implementation of different
implementations with different parameters. The parameterized PIV circuit has been
designed and implemented on an ADM-XRC-5LX FPGA board from Alpha-Data. The computational
speed of the hardware presents an average of 50x speedup in comparison with a software
implementation running on a 3 GHz PC.