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UID:37073-1684751400-1684755000@coe.northeastern.edu
SUMMARY:Mengting Yan's PhD Dissertation Defense
DESCRIPTION:“Integrated Circuit Design Methods for Temperature-based Hardware Trojan Detection and Parametric Frequency Division in Next-Generation Systems-on-a-Chip” \nCommittee Members:\nProf. Marvin Onabajo (Advisor)\nProf. Yong-bin Kim\nProf. Yunsi Fei \nAbstract:\nNew needs for next-generation systems-on-a-chip (SoC) are emerging as the trend of globalization in the semiconductor industry becomes increasingly ubiquitous and the demand for low-power Internet-of-Things (IoT) devices continues to soar. Among various research directions\, this dissertation focuses on enhancing hardware security and on providing low-noise frequency sources for next-generation SoCs. Within this scope\, the described research addresses the challenge to improve on-chip anomaly detection capabilities\, and separately lays a foundation for the design of circuits to reduce the phase noise of on-chip oscillators. \nIn the first part of this dissertation\, an on-chip temperature-based Hardware Trojan (HT) detection system is introduced. The approach to detect inserted HTs relies on thermal profiling of the circuit under test (CUT) and side-channel analysis of the obtained temperature data. On-chip electrothermal coupling is modeled as part of a simulation technique that associates local thermal activities with circuit-level power consumption using a standard electrical simulator. To monitor the thermal profiles on chips with high sensitivity to local temperature changes as well as to enhance the resilience to flicker noise\, a fully-differential temperature sensor equipped with a chopping mechanism has been designed in 130-nm complementary metal-oxide-semiconductor (CMOS) technology\, which has a sensitivity of 840 V/◦C. The simulated temperature sensor output in the presence of noise and process variations is quantized by an analog-to-digital converter (ADC) model and processed using principal component analysis (PCA)\, which allows to determine the minimum detectable Trojan power and the design requirements for the on-chip ADC. With a modeled 8-bit ADC\, simulations of the HT detection system reveal a detection rate of 100% with a Trojan power down to 2.4 μW within the thermal profile of a CUT consuming 508 μW. A prototype 8-bit 1 MS/s successive approximation register (SAR) ADC for such a system was designed in 130-nm CMOS technology\, fabricated\, and tested. The measured effective number of bits (ENOB) is 7.27 bits up to the Nyquist frequency\, with a power consumption of 103.2 μW from a 1.2 V supply. Furthermore\, a 3-step analog calibration loop has been designed to compensate for the voltage offsets within the sensor circuits in the presence of device mismatches and process-temperature variations. The calibration loop settles within 300 μs to complete the offset calibration\, such that the input-referred offset has a standard deviation of 5.86 μV based on Monte Carlo simulations. \nIn the second part of this dissertation\, the on-chip realization of a parametric frequency divider (PFD) is explained. The low-power 2:1 frequency division at sub-6 GHz plays a critical role in on-chip phase noise reduction systems that exhibit nonlinear operations\, indicating promise for future integration into radio frequency (RF) SoCs. In particular\, the first current-driven PFD with an output frequency of 2.4 GHz is introduced\, which consists of three major blocks: (1) a custom PFD driver stage with a buffer to ease input driving\, (2) a purely passive PFD core with inductor-capacitor (LC) resonators\, and (3) an output driving stage with embedded band-pass filtering that suppresses undesirable output harmonics. A prototype PFD chip was fabricated in standard 65-nm CMOS technology\, and the corresponding measurement results are presented to characterize the performance of the new PFD. The minimum required supply voltage for the PFD driver is 1.4 V with an input frequency of 4.8 GHz\, whereas the PFD has an operating frequency range from 4.5 GHz to 5.1 GHz with a supply voltage of 1.5 V. To the best of the author’s knowledge\, the proposed PFD is the first on-chip CMOS implementation for sub-6 GHz applications\, which balances the trade-offs among frequency range\, power consumption\, and chip area constraints.
URL:https://coe.northeastern.edu/event/mengting-yans-phd-dissertation-defense/
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