Faculty
Graduate Students, PhD and MS, in alphabetical order.
Mahsa Bayati
Frank Bruno
Ben Drozdenko
Xin Fang
Chao Liu
Undergraduate Students
Lucas Jaffe
Kevin Langer
Emily Shaffer
Taylor Skilling
Previous PhD Students from NEU (in reverse chronological order of graduation)
and their First/Current Affiliations (if known)
Peter Grossmann
PhD, 2013.
Design and Analysis of Minimum Energy FPGAs
James Brock
PhD, 2012.
An Environment to Support GPU and Multicore Programming for Rapid,
High Performance, Application Deployment
Nicholas Moore
PhD, 2012.
Kernel Specialization for Improved Adaptability and Performance on Graphics Processing Units (GPUs)
MS, 2011.
Vforce: VSIPL++ for Reconfigurable Computing Environments (GPUs)
Abderrahmane Bennis
PhD, August 2010.
Implementing a Highly Parameterized Digital PIV System On Reconfigurable Hardware
Xiaojun Wang
PhD, January 2008.
Variable Precision Floating-Point Divide and Square Root for Efficient
FPGA Implementation of Image and Signal Processing Algorithms
Wang Chen
PhD, May 2007.
Acceleration of the 3D FDTD Algorithm in Fixed-point Arithmetic using Reconfigurable Hardware
MS, August 2003.
An FPGA Implementation of the 2D FDTD Algorithm
Haiqian Yu
PhD, May 2007.
Optimizing Data Intensive Window-based Image Processing
on Reconfigurable Hardware Boards
MS, August 2003.
Memory Architecture of Data Intensive Image Processing Algorithms in
Reconfigurable Hardware
Heather Quinn
PhD, August 2004.
Runtime Tools for Hardware/Software Systems with Reconfigurable Hardware
MS, December 2000. Image Processing Designs in JHDL, a Java-based Hardware Description Language
Juan Carlos Rojas
PhD, August 2003.
Multimedia Macros for Portable Optimized Programs
Silviu Chiricescu
PhD, June 2000.
Parametric Analysis of a Dynamically Reconfigurable Three-Dimensional FPGA
Previous MS Students from NEU (in reverse chronological order of graduation) and their Current Affiliations (if known)
Max Beckett
MS, April 2013.
Project Title: Tasks and Conduits: A Task and Data Parallel Framework for GPU Computing
David Kusinsky
MS, April 2013.
FPGA-based Hyperspectral Covariance Coprocessor for Size, Weight, and Power Constrained Platforms
George Eichinger
MS, April 2012.
CRUSH: Cognitive Radio Universal Software Hardware
Mary Ellen Tie
MS, February 2012.
Accelerating Explicit State Model Checking on an FPGA: PHAST
Devon Yablonski
MS, April 2011.
Numerical Accuracy Differences in CPU and GPGPU Codes
Jainik Kathiara
MS, January 2011.
The Unified Floating Point Vector Co-processor (FPVC)
Scott Bailie
MS, May 2010.
An FPGA Implementation of Incremental Clustering for Radar Pulse Deinterleaving
Sherman Braganza
MS, August 2008.
Phase Unwrapping on Reconfigurable Hardware and Graphics Processors
Ben Cordes
MS, May 2008.
Parallel Backprojection: A Case Study in High Performance Reconfigurable Computing
Albert Conti
MS, May 2007.
A Hardware/Software System for Adaptive Beamforming
Joshua Noseworthy
MS, September 2005.
Enabling Communications Between an FPGA’s Embedded Processor and its Reconfigurable Resources
Shawn Miller
MS, April 2004.
Enabling a Real-time Solution to Retinal Vascular Tracing Using FPGAs.
Srdjan Coric
MS, September 2002.
Parallel-Beam Backprojection: an FPGA Implementation Optimized for Medical Imaging.
Michael Estlick
MS, September 2002
An FPGA Implementation of the K-Means Algorithm for Image Processing.
Pavle Belanovic
MS, June 2002,
Library of Parameterized Modules for Floating-Point Arithmetic with an Example Application.
Natalya Kitaryeva
MS, June 2001,
K-Means Clustering for Color Image Processing on a ReconfigurableHardware Board.
Ali Shankiti
MS, September 1999.
Implementing a RAKE Receiver on an FPGA-based Computer System.
Zixin Yin
MS, December 1998.
Global and Incremental Floorplanning for High-Level Synthesis.
Goran Doncev
MS, June 1998.
Mapping DSP Systems onto FPGAs Using Behavioral Synthesis: A Case Study.
Previous Graduate Students from Cornell
(in reverse chronological order of graduation)
and their First/Current Affiliations (if known)
Valerie Ohm
PhD, May 1999.
Power Estimation for Combinational and Sequential CMOS Circuits using Graph-Based Methods.
Peter Soderquist
PhD, May 1998.
Cache-Sensitive Architectural Optimizations for MPEG-2 Video Decoding.
MS, January 1995. Area and Performance Tradeoffs in Floating-Point Division and Square Root Implementations.
Shantanu Tarafdar
PhD, May 1998.
A Data-Transfer Model for High Level Synthesis and Its Application in Storage and Interconnect Optimization.
Mark Linderman(mark.linderman at rl.af.mil)
PhD, May 1995.
Simulation of Digital Circuits in the Presence of Uncertainty.
Mark Aagaard
(maagaard at uwaterloo.ca)
PhD, January 1995. A Framework for the Specification, Design, and Verification of Pipelines with Structural Hazards.
MS, January 1992. A Formally Verified System for Logic Synthesis.
Yanbing Li
MS, August 1995.
Completed PhD at Princeton University.
Black Sheep of the Lab
(Students who leave without writing up ;-) )