Yixuan He’s PhD Proposal Review

Committee:

Prof. Yong-Bin Kim. Advisor

Prof. Marvin Onabajo

Prof. Lombardi Fabrizio

Abstract:

In order to match the needs of powerful neural networks and meet the hard constraints from hardware, binary neural networks are treated as hardware-friendly deep learning algorithms due to the fact that it can achieve similar inference accuracy with fewer computing resources comparing to traditional convolutional neural networks. As for its VLSI implementations, the computing-in-memory (CIM) technology has been proved to solve the memory-wall bottleneck problem shown in traditional von Neumann machine and can be a perfect choice to implement neural networks with binary data. Therefore, this work proposes a novel time-domain computing-in-memory core that implements XNOR-and-accumulate of binary neural networks with all-digital elements. This new technique uses 8T-SRAM cells to perform XNOR operations inside memory array and accumulates the related XNOR output values in time-domain with specialized racing structures and delay lines. The circuit is built and simulated in Cadence using Samsung 65nm CMOS technology with 1V power supply. The results show correct functionality, 2730 GOPS throughput and 431 TOPS/W power efficiency. With further exploration, the time-domain computation can be a new candidate in the field of in-memory-computing for deep learning applications since it has its own superiorities in terms of throughput, power efficiency in comparison to other mixed-signal or traditional digital methods.