Developing Ultra-Low Power Timing Circuit

Aatmesh Shrivastava

ECE Assistant Professor Aatmesh Shrivastava received a $315K sub-contract on an $800K Phase-I and Phase-II Air Force Research Laboratory (AFRL) grant with escAerospace to develop ultra-low power timing circuit to enable navigation in total GPS denial. Signals from GPS are the world standard for Positioning, Navigation, and Timing (PNT) for both civilian and military needs, but both natural environments, evolving adversary countermeasures, and challenging terrain can seriously weaken or deny access. Commercial and military systems have been developed to meet ever-growing threats. However, these systems tend to be large, heavy, require significant power, and are very expensive. The aim of this project is to develop ultra-low power, precision timing circuit that enables Low Size, Weight, Power and Cost (SWaP-C) PNT positioning in total GPS denial for more than 48 hours.

Related Faculty: Aatmesh Shrivastava

Related Departments:Electrical & Computer Engineering