Kaeli Awarded $250K NSF Grant
ECE Professor David Kaeli was awarded a $250K NSF grant for "Leveraging Intra-chip/Inter-chip Silicon-Photonic Networks for Designing Next-Generation Accelerators".
Abstract Source: NSF
A little over a decade ago, GPUs were fixed-function processors built around a pipeline, dedicated to rendering 3-D graphics. In the past decade, as the potential for GPUs to provide massive compute parallelism became apparent, the software community developed new programming environments (CUDA and OpenCL) to leverage these massively parallel devices. Today, the leading graphics vendors tailor their GPU designs for general-purpose high-performance computing by providing higher compute throughput. While GPUs are able to provide high computational throughput by launching a large number of threads, memory bandwidth and system power continue to be limiting constraints for a number of applications.
This project proposes to explore the use of silicon-photonic link technology to design the intra-chip and inter-chip networks in future GPU/APU systems with the goal of addressing the memory bandwidth constraint. In particular, we will investigate the potential of the silicon-photonic networks to efficiently support the memory hierarchy of a heterogeneous design, which integrates a CPU and a GPU (i.e., an Accelerated Processing Unit (APU)) that share the same memory address space. To this end, using state-of-the-art cycle-based simulators, we will evaluate a range of memory hierarchies and intra-chip/inter-chip silicon-photonic network architectures while running a demanding set of workloads that require high memory bandwidth. Additionally, this work will explore the limits and opportunities to leverage the high-bandwidth density and low latency of the silicon-photonic networks to architect the next generations APU devices that can provide better compute throughput. It is anticipated that the results of this research will clearly demonstrate the advantages of using silicon-photonic intra-chip/inter-chip networks in the memory hierarchy of GPU and APU devices. To catalyze and sustain research in this area of APUs and silicon-photonic networks, an open-source simulator that supports intra-chip and inter-chip silicon-photonic networks will be made available to the wider accelerator/networking research communities.
At a broader level, this work bridges the gap between the heterogeneous systems community and the on-chip/off-chip networks community and opens multiple opportunities for education and outreach.