New Analog Chip Powers Next-Gen Radar
ECE Assistant Professor Aravind Nagulu’s lab published their work on “Fully Analog, Multi-Lag, RF Correlators for Code-Domain Radars Using Margin Propagation” in the IEEE Journal of Solid-State Circuits.
Abstract:
We present a fully analog, multiplier-free, sampled-domain RF correlator to achieve high energy efficiency for radar workloads. The RF correlator employs a split-source follower architecture that leverages the margin propagation (MP) computing paradigm in the sampled domain. As a proof of concept, we implement a 256×256 fully analog cross correlator in a 22 nm SOI-CMOS process. Large analog delays are realized using a sampling-based approach, and the design incorporates a compact, power and area-efficient four-transistor compute cell. The fabricated IC achieves: 1) input and template data rates up to 4GS/s; 2) single-shot 256-point cross correlations across 256 lags, enabling full 256×256 cross correlation; 3) >8 bit compute accuracy; 4) energy efficiency of 1000 1b-TOPS/W and 5) compute density of 1.3 1b-TOPS/mm2 per cell. The MP correlator demonstrates robust performance across process–voltage–temperature (PVT) variations and is deployed in a code-domain radar system with multi-user operation, validating system-level feasibility.