Siddhartha Nath

About

Sid Nath joined Intel in Aug 2022 as Principal Engineer and Director of ML Initiatives in PESG-DDI, where he architects and leads ML initiatives for PPA and productivity in the SD construction space. Prior to joining Intel, Sid was a Sr. Research Scientist at Nvidia Research from Aug 2021-Aug 2022, and Sr. Staff ML Lead at Synopsys from Aug 2016-Aug 2021. Sid has productized multiple ML features in EDA tools that have been used for tapeout by top semiconductor design companies at 7nm and below. Sid serves as the TPC member of DAC, ICCAD, ISPD, TCAD, TODAES and has one best paper award and multiple best paper nominations at DAC, ISPD and ICCAD. Sid obtained his PhD in Computer Science from UC San Diego in Aug 2016, has over 35 publications in top-tier conferences and journals on design automation and over eight granted US patents with several more in the pipeline.

Sid’s research interests are in machine learning, combinatorial optimization and mathematical programming. Sid teaches graduate classes on design and analysis of algorithms and introduction to machine learning at Northeastern Univ since Fall 2022 and Santa Clara Univ since Fall 2021.

Selected Publications

• Y.-C. Lu, S. Nath. S. Pentapati and S. K. Lim, “ECO-GNN: Signoff Power Prediction using Graph Neural Networks with Subgraph
  Approximation”, ACM Transactions on Design Automation of Electronics Systems (TODAES) (2022), to appear.
• P. Agrawal, M. Broxterman, B. Chatterjee, P. Cuevas, K. H. Hayashi, A. B. Kahng, P. K. Myana and S. Nath, “Optimal Scheduling and
  Allocation for IC Design Management and Cost Reduction”, ACM Transactions on Design Automation of Electronics Systems (TODAES)
  22(4) (2017), pp. 1-30.
• A. B. Kahng, B. Lin and S. Nath, “ORION3.0: A Comprehensive NoC Router Estimation Tool”, IEEE Embedded Systems Letters 7(2) (2015),
  pp. 41-45.
• T.-B. Chan, A. B. Kahng, J. Li, S. Nath and B. Park, “Optimization of Overdrive Signoff in High-Performance and Low-Power ICs”, IEEE
  Transactions on Very Large Scale Integration (VLSI) Systems 23(8) (2014), pp. 1552-1556.
• M. Arora, S. Nath, S. Mazumdar, S. Baden and D. Tullsen, “Redefining the Role of CPU in the Era of CPU-GPU Integration”, IEEE Micro,
  Nov-Dec, 2012.

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