ECE PhD Dissertation Defense: Hongjia Li

PhD Dissertation Defense: Automation Design and DNN Acceleration Frameworks: from software implementation to hardware physical design

Hongjia Li

Location: Northeastern Zoom Link

Abstract: With the breakthrough of Deep Neural Networks (DNNs) in the past decade, neural network-based computer vision has made huge progress, achieving exceptional performance. Tasks such as object detection, activity detection, and medical diagnosis are deployed in a wide range of applications, including autonomous driving, robot vision and training, human-computer interaction, and augmented reality. To increase the demand of application accuracy, DNN models are tuned to large scales by adding more parameters and layers. Meanwhile, mobile devices are rapidly becoming the central computer and carrier for deep learning tasks. However, real-time execution has been limited due to the computation/storage resource constraints on mobile devices.
The first part of this dissertation, I will present our unified real-time mobile acceleration of DNNs framework, seamlessly integrating hardware-friendly, structured model compression with mobile-targeted compiler optimization. The goal of our framework is to provide an unprecedented, real-time performance of such large-scale neural network inference using simply off-the-shelf mobile devices. Our proposed fine-grained block-based pruning scheme can be universally applicable to all types of DNN layers, such as CONV layers with different kernel sizes and fully connected layers. Different weight pruning schemes, such as unstructured pruning, filter/column pruning, and our block-based pruning, are analyzed and compared given the specific deep learning problems. To validate our framework, various applications are implemented and demonstrated, object detection, medical diagnosis. All applications can achieve real-time inference on mobile devices, outperforming the current mobile acceleration framework by up to 6.7X in speed.
For the second part of this dissertation, I will dive into an efficient automate framework for Adiabatic Quantum-Flux-Parametron (AQFP) technology, meeting the unique features and constraints. Superconductive electronics (SCE) based on the Josephson junction (JJ) single flux quantum (SFQ) logic cells have evolved into a within-reach “beyond-CMOS” technology. Placement is the primary step in physical design of the electronic systems as it directly affects the maximum frequency and routability of circuits. Algorithms for global placement, the core step in the placement process, typically minimize the total wirelength of a design as the main objective as it indirectly affects the routability and timing of circuits. Although minimizing the total wirelength improves the timing of the circuit in general, it does not directly target optimizing the delay of timing critical paths. Timing and routability driving placement methods are therefore needed. The currently mature design automation tools for CMOS cannot be directly applied to the design of superconducting electronics. In this dissertation, I will present our proposed timing-aware AQFP-specific placement and routing framework, given a path balanced AQFP netlist with clock phases. The proposed framework will reduce the solution complexity by making effective use of the row-wise placement/routing opportunity as each AQFP cell is assigned to a specific row (clock phase).