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ECE PhD Dissertation Defense: Mahmoud Ibrahim
July 23, 2021 @ 10:00 am - 11:00 am
PhD Dissertation Defense: Low-Power Integrated Circuit Design for Wireless Devices in the Internet of Things
Abstract: Numerous integrated sensing devices are under development for wireless medical diagnostic and monitoring applications. However, the data rates of wireless devices connected to the Internet of Things are limited and strongly depend on the available power. This research addresses the need for circuit-level design methods to enable higher data rates with lower power consumption in order to facilitate the proliferation of wireless devices that can overcome the speed-power conundrum. The potential applications include continuous-time monitoring of physiological signals, where increased data rates imply the ability to exchange more information during the same time, more accurate data, and/or data from a greater number of sites associated with each wireless node.
An energy-efficient binary frequency shift keying (BFSK) transmitter architecture for biomedical applications is introduced as the first part of this dissertation research. To achieve low power consumption with higher data rates, the novel transmitter architecture leverages image rejection techniques to generate each of the two tones of the transmitted BFSK signal while keeping the phase-locked loop (PLL) oscillator frequency unchanged, and thus maintaining low PLL power and overall transmitter power. A fabricated prototype chip in 130nm complementary metal-oxide-semiconductor (CMOS) technology achieves data rates up to 10 Mbps while consuming 180 µW with up to -20 dBm output power according to Medical Implant Communication System (MICS) band requirements. The measurement results confirm state-of-the-art energy-efficient performance with 18 pJ/bit.
As a natural continuation of the first part of this research, a complementary receiver architecture is described in the second part of this dissertation to provide full transceiver capabilities. The new receiver design approach takes advantage of the transmitted signal characteristics by using both the frequency information and phase information to demodulate the received digital bits. This design method results in improved sensitivity with reduced power consumption through relaxed receiver block specification requirements. The custom-designed receiver circuits include a new low-noise amplifier (LNA) topology for energy-efficient antenna impedance matching, and a single mixer circuit that realizes the signal down-conversion with differential in-phase and quadrature-phase baseband output signals to circumvent the complexity associated with two mixers and to save power. Measurement results of the fabricated receiver in 65nm CMOS technology show a sensitivity of -82 dBm with an input signal at 10 Mbps centered around 416 MHz. With a power consumption of 610 µW and an energy efficiency of 61 pJ/bit, this receiver architecture displays state-of-the-art performance with respect to data rate, power and sensitivity compared to other receivers in the same frequency range.
In addition to the new transmitter and receiver architectures, a large-signal transconductance linearization technique is presented as part of this dissertation research to extend the dynamic range of analog baseband filters. Furthermore, a low-power sinusoidal signal generation technique is introduced and analyzed, which is a versatile and essential component of the transmitter design approach.