ECE PhD Proposal Review: Mengting Yan

PhD Proposal Review: Circuit Design Methods for Temperature-based Hardware Trojan Detection and Parametric Frequency Division in Next-Generation Systems-on-a-Chip

Mengting Yan

Location: Zoom Link

Abstract: With the increasing costs and globalization in the semiconductor industry over the past years, the ongoing trends to disperse integrated circuit (IC) design, fabrication and testing tasks among different design centers and manufacturers are becoming more common and inevitable. As a soaring number of ICs are fabricated around the world, the increasing risks associated with hardware Trojan (HT) insertions have been identified as a growing concern in military systems, medical applications, wireless cryptography, etc. This research introduces an integrated system-level on-chip countermeasure to malicious HT insertions, which is founded on power sensing and integrated circuit design. The approach addresses the corresponding design considerations of analog temperature sensors, on-chip quantization of signals and machine learning-based data analysis.
An on-chip temperature-based HT detection system is proposed in the first part of this dissertation research. The approach to detect inserted HTs relies on thermal profiling of the circuit-under-test (CUT) and side-channel analysis of the obtained thermal data. Hence, a system that includes the CUT, modeled HT, temperature sensing circuitry and an on-chip ADC will be implemented and evaluated through simulations and measurements. On-chip electro-thermal coupling is modeled as part of the simulation technique, which associates local thermal activities with circuit-level power consumption using a standard electrical simulator. To monitor the thermal profiles on chips with high sensitivity to local temperature changes and the resilience to flicker noise, a fully-differential temperature sensor equipped with a chopping mechanism has been designed in 130-nm CMOS technology, which has a sensitivity of 840 V/°C over a linear dynamic range of ±1°C. The simulated temperature sensor output in the presence of noise and process variations is quantized by an ideal ADC model and processed using principal component analysis (PCA), which allows to determine the minimum detectable Trojan power and the design requirements for the on-chip ADC. With a modeled 8-bit ideal ADC, the proposed HT detection system shows a detection rate of 100% with a Trojan power down to 2.4 µW within the thermal profile of a CUT consuming 508 µW. A prototype 8-bit 1 MS/s SAR ADC was designed in 130-nm CMOS technology, fabricated, and tested. The measured effective number of bits (ENOB) is 7.27 bits up to the Nyquist frequency with a power consumption of 103.2 µW from a 1.2 V supply.
Another part of this dissertation research addresses the need for low-power 2:1 frequency division at sub-6 GHz frequencies for radio frequency (RF) systems-on-a-chip (SoCs). In particular, a differential 2:1 parametric frequency divider (PFD) with an output frequency of 2.4 GHz and an input voltage range of 450-890 mV at 4.8 GHz is being designed in 65-nm CMOS technology, which mainly consists of passive on-chip components and consumes zero static power. The proposed PFD is the first on-chip CMOS implementation for sub-6 GHz applications, which balances the trade-offs among frequency range, power consumption, and chip area constraints. As an important part of this dissertation, the performance of the proposed PFD will be validated with measurements of a prototype chip fabricated in standard 65-nm CMOS technology.