Yiyue Jiang’s PhD Proposal Review

“FPGA-based Accelerator of Neural Networks for Digital Predistortion”

Committee:

Prof. Miriam Leeser (Advisor)

Prof. John Dooley

Prof. Stefano Basagni

Abstract:

Power Amplifiers (PAs) are an essential part of wireless communications.

As wireless standards evolve and become more demanding,  the requirements for PAs change as well.  Specifically, PAs need to balance linearity and energy efficiency while adhering to 5G wireless standards and beyond. PA behaviors differ based on several criteria, including the type of PA, power levels, and the environment. To overcome the nonlinear behavior of a PA, a flexible system to achieve digital predistortion (DPD) is required that can rapidly adapt to its environment.

In many situations, traditional methods such as the memory polynomial model cannot adapt to all these factors. Neural networks have been used for some years in RF and microwave engineering. Early work demonstrated the suitability of neural networks to model complicated active device characteristics. Current neural network based DPD systems all do the training offline and are therefore not real-time systems. To reduce the cost to upgrade hardware and to provide more flexibility to different power amplifiers’ linearization needs, a specific neural network based reconfigurable, adaptive, and real-time digital predistortion system is proposed. This system targets Zynq All Programmable System on Chip (SoC) devices which feature an ARM processor and FPGA together with RF frontend on the same chip. The system proposed in this research combines real-time DPD with on-chip training. Furthermore, most research on FPGA based inference accelerators targets classification problems with probability output. There is no accelerator working on the signal processing problem focusing on sample-by-sample output. Our proposed system is optimized in both algorithm and implementation targeting sample-by-sample processing with high accuracy and real-time efficiency.