Saion Roy
Postdoctoral Research Associate,
Electrical and Computer Engineering
Research Focus
Integrated Circuits, Machine Learning Hardware, and Hardware Security
About
Saion K. Roy (Member, IEEE) received the B.Tech. and M.Tech. degrees in Electronics and Electrical
Communication Engineering from the Indian Institute of Technology Kharagpur, India, in 2018, and the Ph.D. degree in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign, USA, in 2024. His doctoral research focused on emerging non-volatile memory (eNVM)-based in-memory computing for machine-learning accelerators, with an emphasis on energy-efficient integrated-circuit design. He is currently a Postdoctoral Research Associate at Northeastern University, where his research lies at the intersection of integrated circuits and hardware security, with a focus on secure and energy-efficient machine-learning accelerators. His work has appeared in leading conferences and journals, including AsiaCCS, ICCAD, IEDM, ESSCIRC, CICC, ISCAS, TCAD, JSSC, JxCDC, and OJ-SSCS. He has also served on the Technical Program Committee for conferences including ISCA, MICRO, and ICCAD.
Education
- PhD, Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 2024.
- B.Tech. and M.Tech., Electronics and Electrical Communication Engineering, Indian Institute of
Technology Kharagpur, 2018.
Research Overview
Integrated Circuits, Machine Learning Hardware, and Hardware Security
His research lies at the intersection of integrated circuits and hardware security, with a focus on secure and energy-efficient machine-learning accelerators. His work examines how algorithm mapping, microarchitectural choices, and silicon implementation shape efficiency, robustness, and the hardware attack surface. His goal is to develop secure-by-design machine-learning systems through algorithm–architecture–circuit co-design, treating security and privacy as first-class constraints alongside accuracy, energy, and reliability.
Selected Publications
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Tianhong Xu, Saion K. Roy, Ruyi Ding, A. Adam Ding, and Yunsi Fei. SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon. ACM SIGSAC Conference on Computer and Communications Security (CCS), 2026, to appear.
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Saion K. Roy*, Yufei Wang*, A. Adam Ding, and Yunsi Fei. ROBBIN: Rowhammer-Based Backdoor Injection during Inference. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026, to appear.
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Saion K. Roy and Naresh R. Shanbhag. Comprehending the Energy-Accuracy-Security Trade-offs in Embedded Non-Volatile In-Memory Computing Architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.
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Saion K. Roy, Ziyue Zhang, A. Adam Ding, and Yunsi Fei. Attack from Shadows: Unsupervised Side-channel Transfer Learning across Devices and Modalities. 21st ACM Asia Conference on Computer and Communications Security (AsiaCCS), 2026.
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Saion K. Roy and Naresh R. Shanbhag. The Energy-Accuracy-Security Trade-off in Resistive In-memory Architectures. IEEE International Electron Devices Meeting (IEDM), 2024.
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Saion K. Roy and Naresh R. Shanbhag. On the Security Vulnerabilities of MRAM-based In-Memory Computing Architectures against Model Extraction Attacks. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2024.
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Saion K. Roy, Han-Mo Ou, Mostafa G. Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan K. Hanumolu, and Naresh R. Shanbhag. Compute SNDR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation. IEEE Journal of Solid-State Circuits (JSSC), 2024.
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Saion K. Roy and Naresh R. Shanbhag. Energy-Accuracy Trade-offs for Resistive In-Memory Computing Architectures. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2024.
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Saion K. Roy, Han-Mo Ou, Mostafa G. Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan K. Hanumolu, and Naresh R. Shanbhag. Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation. IEEE European Solid-State Circuits Conference (ESSCIRC), 2023.
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Naresh R. Shanbhag and Saion K. Roy. Benchmarking In-memory Computing Architectures. IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS), 2022.
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Naresh R. Shanbhag and Saion K. Roy. Comprehending In-memory Computing Trends via Proper Benchmarking. IEEE Custom Integrated Circuits Conference (CICC), 2022.
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Saion K. Roy, Ameya D. Patil, and Naresh R. Shanbhag. Fundamental Limits on the Computational Accuracy of Resistive Crossbar-based In-memory Architectures. IEEE International Symposium on Circuits and Systems (ISCAS), 2022.